DPU Hardware Design
Principal drivers of the DPU design are
- optimum use of the allocated telemetry rate,
- single-failure tolerance for all functions serving more than one sensor,
- independence of availability of radiation hardened parts.
The primary data rate of all three detectors exceeds the maximum spacecraft telemetry rate (20 kbits-1) by more than three orders of magnitude. Reducing the amount of scientific data is therefore a fundamental need. It is achieved at two levels: hardware-based integration within the sensor electronics, and subsequent S/W processing by
- spectrum windowing,
- averaging, resulting in degraded mass and/or time resolution,
- lossless compression (modified Rice PSI14), and task specific lossy compression.
All S/W processing is performed in the DPU by a 32-bit digital signal processor (DSP, TSC21020F) with a large and fast SRAM memory (3 Mbyte program, 8 Mbyte data memory).
All DPU functions are duplicated and organized into two independent (cold redundant) branches except the three sensor interfaces and the hard core for selection of the active branch.
DPU Software Design
The DPU S/W is based on the real-time multitasking operating system Virtuoso (Eonic Systems) that provides:
- preemptive, event-driven scheduling,
- dynamically prioritized tasks,
- synchronization and communication facilities (semaphores, mailboxes, queues, timers),
- dynamic memory management, and
- handling of multilevel device interrupts.
All S/W tasks are grouped in a layer model with 6 layers:
(5) Scientific Software,
(4) Operation Control (command execution, emergency mode, In-flight calibration, etc.),
(3S) Service Functions (command interpreter, housekeeping collection, data compression, etc.),
(3) Element Functions (detector on/off, data acquisition / handling, etc.),
(2) Subelement Functions (direct control of subelements), and
(1) Low Level S/W (H/W driver, I/O control).